Chinese chipmaker ships record-breaking chips: YMTC quietly begins shipping 5th Gen 3D TLC NAND

Yangtze Memory Technologies Co. (YMTC) has quietly started to ship its 5th-Gen 3D NAND memory with 294 layers in total as well as 232 active layers, and analysts from TechInsights have managed to obtain these ICs for analysis, reports @Jukanlosreve. As it turns out, YMTC has successfully increased bit density to the levels of its industry peers, while it also achieved the highest vertical gate density despite sanctions against the company imposed by the U.S. Yet, there are a couple of catches. 

The chip achieves a remarkable total number of layers (or gates per vertical NAND string) — 294 — which TechInsights says is the highest for current commercial products. The number of active layers of YMTC’s 5th Generation 3D NAND is expected to be 232, the same as in the case of the company’s 4th-Gen 3D NAND, which has 253 layers in total. The increase in the total number of layers could be a way to improve yield by increasing redundancy or enabling certain features.

Like its predecessors, the 3D NAND device uses string stacking. However, it is unclear whether Yangtze Memory uses two ~147-layer arrays or multiple arrays with fewer layers. In any case, the 294 layers (including active and dummy layers) are an important milestone for YMTC and the whole flash memory industry.

232 active layers is not a record layer count for 3D NAND, but it is in line with the rivals. Only SK hynix’s 321-layer 9th Generation 3D NAND has more than 300 active layers these days, though its shipments will start in the first half of this year. The achievement of 294 total layers (or gates per vertical NAND string) not only positions YMTC as a strong contender in the global NAND flash memory market but also signals significant progress in China’s semiconductor industry amid major U.S. sanctions. 

In terms of bit density, YMTC’s 5th Gen 3D TLC device surpasses 20 Gb/mm², which seems to be in line with what SK hynix’s G9 3D TLC NAND IC offers and is just slightly below the 22.9 Gb/mm² featured by Kioxia’s/Western Digital BiCS8 3D QLC NAND device, according to TechInsights. YMTC’s competitors have yet to introduce 3D TLC NAND chips with density levels similar to those of the market.

With its 5th Generation 232-layer 3D TLC NAND devices, Yangtze Memory continues to use hybrid bonding technology to connect the flash array with CMOS logic and interface, which enables the company to maximize storage density and I/O performance for the best SSDs that usually surpasses what is offered by rivals. YMTC’s 3D TLC NAND ICs use Xtacking 4.0 architecture. 

YMTC’s 232-layer 3D NAND with 294 gates per NAND string marks a significant milestone for the company specifically and the Chinese memory industry more broadly. It is noteworthy that Yangtze Memory has not formally announced its 5th Generation 3D TLC NAND devices but has instead quietly begun their volume shipments. This move was possibly made to avoid drawing the attention of the U.S. government and risking further sanctions.